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DATA SHEET
MOS INTEGRATED CIRCUIT
PD4564441, 4564841, 4564163
64M-bit Synchronous DRAM 4-bank, LVTTL
Description
The PD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4, 1,048,576 x16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock.
www..com The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Quad internal banks controlled by A12 and A13 (Bank Select) * Byte control (x16) by LDQM and UDQM * Programmable Wrap sequence (Sequential / Interleave) * Programmable burst length (1, 2, 4, 8 and full page) * Programmable /CAS latency (2 and 3) * Automatic precharge and controlled precharge * CBR (auto) refresh and self refresh * x4, x8, x16 organization * Single 3.3 V 0.3 V power supply * LVTTL compatible inputs and outputs * 4,096 refresh cycles / 64 ms * Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0149N10 (Ver.1.0) (Previous No. M12621EJCV0DS00) Date Published August 2001 (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
PD4564441, 4564841, 4564163
Ordering Information
Part number Organization (word x bit x bank) 4M x 4 x 4 Clock frequency MHz (MAX.) 125 100 100 2M x 8 x 4 125 100 100 1M x 16 x 4 125 100 100 Package 54-pin Plastic TSOP (II) (10.16mm (400))
PD4564441G5-A80-9JF PD4564441G5-A10-9JF PD4564441G5-A10B-9JF PD4564841G5-A80-9JF PD4564841G5-A10-9JF PD4564841G5-A10B-9JF PD4564163G5-A80-9JF PD4564163G5-A10-9JF PD4564163G5-A10B-9JF
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
Part Number
[ x4, x8 ]
PD4564841G5 - A80
NEC Memory Synchronous DRAM Memory density 64 : 64M bits Minimum cycle time 80 : 8 ns (125 MHz) 10 : 10 ns (100 MHz) 10B : 10 ns (100 MHz)
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4 : x4 8 : x8
Number of banks 4 : 4 banks
Interface 1 : LVTTL
Low voltage A : 3.3 0.3 V
Package
[ x16 ]
Organization 16 : x16 Number of banks and Interface 3 : 4 banks, LVTTL
163
G5 : TSOP (II)
Data Sheet E0149N10
3
PD4564441, 4564841, 4564163
Pin Configurations
/xxx indicates active low signal. [PD4564441] 54-pin Plastic TSOP (II) (10.16mm (400)) 4M words x 4 bits x 4 banks
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VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss NC VssQ NC DQ3 VccQ NC NC VssQ NC DQ2 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
A0 to A13 CLK CKE /CS /RAS /CAS /WE DQM VCC VSS VCCQ VSSQ NC
Note
: Address inputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : Write enable : DQ mask enable : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection Note A0 to A11 : Row address inputs A0 to A9 : Column address inputs A12, A13 : Bank select
DQ0 to DQ3 : Data inputs / outputs
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
[PD4564841] 54-pin Plastic TSOP (II) (10.16mm (400)) 2M words x 8 bits x 4 banks
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VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ7 VssQ NC DQ6 VccQ NC DQ5 VssQ NC DQ4 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
A0 to A13 CLK CKE /CS /RAS /CAS /WE DQM VCC VSS VCCQ VSSQ NC
Note
: Address inputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : Write enable : DQ mask enable : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection Note A0 to A11 : Row address inputs A0 to A8 : Column address inputs A12, A13 : Bank select
DQ0 to DQ7 : Data inputs / outputs
Data Sheet E0149N10
5
PD4564441, 4564841, 4564163
[PD4564163] 54-pin Plastic TSOP (II) (10.16mm (400)) 1M words x 16 bits x 4 banks
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VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ15 VssQ DQ14 DQ13 VccQ DQ12 DQ11 VssQ DQ10 DQ9 VccQ DQ8 Vss NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
A0 to A13 CLK CKE /CS /RAS /CAS /WE LDQM UDQM VCC VSS VCCQ VSSQ NC
Note
: Address inputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : Write enable : Lower DQ mask enable : Upper DQ mask enable : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection Note A0 to A11 : Row address inputs A0 to A7 : Column address inputs A12, A13 : Bank select
DQ0 to DQ15 : Data inputs / outputs
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
Block Diagram
CLK CKE
Clock Generator Bank D Bank C Bank B Row Address Buffer & Refresh Counter
Address
Mode Register
Row Decoder
Bank A
Sense Amplifier
Command Decoder Control Logic
/CS /RAS /CAS www..com /WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
Data Sheet E0149N10
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PD4564441, 4564841, 4564163
CONTENTS
1. 2. 3. 4.
Input / Output Pin Function ........................................................................................................... 10 Commands ...................................................................................................................................... 11 Simplified State Diagram ............................................................................................................... 14 Truth Table ...................................................................................................................................... 15
4.1 Command Truth Table ............................................................................................................................ 15 4.2 DQM Truth Table ..................................................................................................................................... 15 4.3 CKE Truth Table ...................................................................................................................................... 15 4.4 Operative Command Table .................................................................................................................... 16 4.5 Command Truth Table for CKE ............................................................................................................. 19
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5. 6. 7.
Initialization ..................................................................................................................................... 20 Programming the Mode Register .................................................................................................. 21 Mode Register ................................................................................................................................. 22
7.1 Burst Length and Sequence ................................................................................................................. 23
8. 9.
Address Bits of Bank-Select and Precharge ................................................................................ 24 Precharge ........................................................................................................................................ 25
10. Auto Precharge ............................................................................................................................... 26
10.1 10.2 Read with Auto Precharge .................................................................................................................. 26 Write with Auto Precharge ................................................................................................................. 27
11. Read / Write Command Interval .................................................................................................... 28
11.1 11.2 11.3 11.4 Read to Read Command Interval ....................................................................................................... 28 Write to Write Command Interval ....................................................................................................... 28 Write to Read Command Interval ....................................................................................................... 29 Read to Write Command Interval ....................................................................................................... 30
12. Burst Termination ........................................................................................................................... 31
12.1 12.2 Burst Stop Command ......................................................................................................................... 31 Precharge Termination ....................................................................................................................... 32 12.2.1 12.2.2 Precharge Termination in READ Cycle ................................................................................... 32 Precharge Termination in WRITE Cycle ................................................................................. 33
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
13. Electrical Specifications ................................................................................................................ 34
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 AC Parameters for Read Timing ........................................................................................................ 39 AC Parameters for Write Timing ........................................................................................................ 41 Relationship between Frequency and Latency ................................................................................. 42 Mode Register Set ............................................................................................................................... 43 Power on Sequence and CBR (auto) Refresh ................................................................................... 44 /CS Function ........................................................................................................................................ 45 Clock Suspension during Burst Read (using CKE Function) ......................................................... 46 Clock Suspension during Burst Write (using CKE Function) ......................................................... 48 Power Down Mode and Clock Mask .................................................................................................. 50
13.10 CBR (auto) Refresh ............................................................................................................................. 51 13.11 Self Refresh (Entry and Exit) .............................................................................................................. 52 13.12 Random Column Read (Page with Same Bank) ............................................................................... 53 13.13 Random Column Write (Page with Same Bank) ............................................................................... 55 13.14 Random Row Read (Ping-Pong Banks) ............................................................................................ 57
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13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 59 13.16 Read and Write .................................................................................................................................... 61 13.17 Interleaved Column Read Cycle ......................................................................................................... 63 13.18 Interleaved Column Write Cycle ......................................................................................................... 65 13.19 Auto Precharge after Read Burst ....................................................................................................... 67 13.20 Auto Precharge after Write Burst ....................................................................................................... 69 13.21 Full Page Read Cycle .......................................................................................................................... 71 13.22 Full Page Write Cycle .......................................................................................................................... 73 13.23 Byte Write Operation ........................................................................................................................... 75 13.24 Burst Read and Single Write (Option) ............................................................................................... 76 13.25 Full Page Random Column Read ....................................................................................................... 77 13.26 Full Page Random Column Write ....................................................................................................... 78 13.27 PRE (Precharge) Termination of Burst .............................................................................................. 79
14. Package Drawing ............................................................................................................................ 81 15. Recommended Soldering Conditions .......................................................................................... 82 16. Revision History ............................................................................................................................. 83
Data Sheet E0149N10
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PD4564441, 4564841, 4564163
1. Input / Output Pin Function
Pin name CLK CKE Input / Output Input Input Function CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the PD4564xxx suspends operation. When the PD4564xxx is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. Row Address is determined by A0 - A13 at the CLK (clock) rising edge in the active command cycle. It does not depend on the bit organization. Column Address is determined by A0 - A9 at the CLK rising edge in the read or write command cycle. It depends on the bit organization: A0 - A9 for x4 device, A0 - A8 for x8 device, A0 - A7 for x16 device. A12 and A13 are the bank select signal (BS). In command cycle, A12 and A13 low select bank A, A12 low and A13 high select bank B, A12 high and A13 low select bank C and then A12 and A13 high select bank D. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by A12 and A13 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. DQM controls I/O buffers. In x16 products, UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ pins have the same function as I/O pins on a conventional DRAM. VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers.
/CS
Input
/RAS, /CAS, /WE
Input
A0 - A13
Input
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DQM, UDQM, LDQM
Input
DQ0 - DQ15 VCC, VSS, VCCQ, VSSQ
Input / Output (Power supply)
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
2. Commands
Mode register set command (/CS, /RAS, /CAS, /WE = Low) The PD4564xxx has a mode register that defines how the device operates. In this command, A0 through A13 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2 CLK (tRSC) following this command, the PD4564xxx cannot accept any other commands.
Fig.1 Mode register set command
CLK CKE /CS /RAS /CAS /WE A12, A13 A10 Add H
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Activate command (/CS, /RAS = Low, /CAS, /WE = High)
Fig.2 Row address strobe and bank activate command
CLK
The PD4564xxx has four banks, each with 4,096 rows. This command activates the bank selected by A12 and A13 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling.
CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10 Add
Row Row
Precharge command Fig.3 Precharge command (/CS, /RAS, /WE = Low, /CAS = High)
CLK
This command begins precharge operation of the bank selected by A12 and A13 (BS). When A10 is High, all banks are precharged, regardless of A12 and A13. When A10 is Low, only the bank selected by A12 and A13 is precharged. After this command, the PD4564xxx can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's /RAS rising.
CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10
(Precharge select)
Add
Data Sheet E0149N10
11
PD4564441, 4564841, 4564163
Write command (/CS, /CAS, /WE = Low, /RAS = High)
CLK
Fig.4 Column address and write command
If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks.
CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10 Add Col.
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Read command (/CS, /CAS = Low, /RAS, /WE = High)
Fig.5 Column address and read command
CLK
Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address.
CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10 Add Col.
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the PD4564xxx cannot accept any other command.
Fig.6 CBR (auto) refresh command
CLK CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10 Add
12
Data Sheet E0149N10
PD4564441, 4564841, 4564163
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the PD4564xxx exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. Fig.7 Self refresh entry command
CLK CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
A10 Add
Burst stop command
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Fig.8 Burst stop command in Full Page Mode
CLK
(/CS, /WE = Low, /RAS, /CAS = High) This command can stop the current burst operation.
CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10 Add
No operation (/CS = Low, /RAS, /CAS, /WE = High) This command is not an execution command. No operations begin or terminate by this command.
Fig.9 No operation
CLK CKE /CS /RAS /CAS /WE A12, A13
(Bank select)
H
A10 Add
Data Sheet E0149N10
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PD4564441, 4564841, 4564163
3. Simplified State Diagram
Self Refresh
SE LF Fe xit
L SE
Mode Register Set
MRS IDLE
REF
CBR (auto) Refresh
CK
ACT
E
CK
E
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Power Down
CKE ROW ACTIVE
BS T
Re
CKE
BS ad T
Active Power Down
Wr
WRITE SUSPEND
CKE WRITE CKE
Au
to
pre
ite
wit h ch arg
Write
W
e rit
Au h wit e ad rg Re cha pre to PRE
Read
Read
e
CKE READ CKE
Write
READ SUSPEND
PR E( Pre cha rge ter min atio n)
WRITEA SUSPEND
CKE WRITEA CKE
CKE READA CKE
n) atio min ter rge cha Pre E( PR
READA SUSPEND
POWER ON
Precharge
Precharge
Automatic sequence Manual input
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
4. Truth Table
4.1 Command Truth Table
Function Symbol n-1 Device deselect No operation Burst stop Read Read with auto precharge Write Write with auto precharge Bank activate Precharge select bank Precharge all banks www..com Mode register set DESL NOP BST READ READA WRIT WRITA ACT PRE PALL MRS H H H H H H H H H H H CKE n x x x x x x x x x x x H L L L L L L L L L L x H H H H H H L L L L x H H L L L L H H H L x H L H H L L H L L L /CS /RAS /CAS /WE A12, A13 x x x V V V V V V x L x x x L H L H V L H L A10 A11, A9 - A0 x x x V V V V V x x V
Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid data input 4.2 DQM Truth Table
Function Symbol n-1 Data write / output enable Data mask / output disable Upper byte write enable / output enable Lower byte write enable / output enable Upper byte write inhibit / output disable Lower byte write inhibit / output disable ENB MASK ENBU ENBL MASKU MASKL H H H H H H CKE n x x x x x x L x H x U L H x L x H DQM L
Remark H = High level, L = Low level, x = High or Low level (Don't care) 4.3 CKE Truth Table
Current state Function Symbol n-1 Activating Any Clock suspend Idle Idle Self refresh Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR (auto) refresh command Self refresh entry Self refresh exit REF SELF H L L H H L L Idle Power down Power down entry Power down exit H L L CKE n L L H H L H H L H H x x x L L L H x H L x x x L L H x x x H x x x L L H x x x H x x x H H H x x x H x x x x x x x x x x /CS /RAS /CAS /WE Address
Remark H = High level, L = Low level, x = High or Low level (Don't care)
Data Sheet E0149N10
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PD4564441, 4564841, 4564163
4.4 Operative Command Table
Current state Idle
Note1
(1/3)
Address x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Nop or power down Nop or power down ILLEGAL ILLEGAL Row activating Nop CBR (auto) refresh or self refresh Mode register accessing Nop Nop Begin read : Determine AP Begin write : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Terminate burst, new read : Determine AP Terminate burst, start write : Determine AP ILLEGAL Terminate burst, precharging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read : Determine AP Terminate burst, new write : Determine AP ILLEGAL Terminate burst, precharging ILLEGAL ILLEGAL 7, 8 7 3 9 7 7, 8 3 5 5 3 6 4 Notes 2 2 3 3
/CS /RAS /CAS /WE H L L L L L L L x H H H L L L L x H H H L L L L x H H H H L L L L x H H H H L L L L x H L L H H L L x H L L H H L L x H H L L H H L L x H H L L H H L L x x H L H L H L x x H L H L H L x H L H L H L H L x H L H L H L H L
Row active
H L L L
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L L L L
Read
H L L L L L L L L
Write
H L L L L L L L L
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
(2/3)
Current state Read with auto precharge /CS /RAS /CAS /WE H L L L L L L L L Write with auto precharge H x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L x H L H L H L H L x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code Address Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Action Continue burst to end Precharging Continue burst to end Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Write recovering with auto precharge Continue burst to end Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP Nop Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter bank active after tRCD Nop Enter bank active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 3 3 3, 10 3 3 3 3 3 3 3 3 3 3 3 3 Notes
L L L L L L L L Precharging H L L L L L L L L Row activating H L L L L L L L L
NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
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Data Sheet E0149N10
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PD4564441, 4564841, 4564163
(3/3)
Current state Write recovering /CS /RAS /CAS /WE H L L L L L L L L Write recovering with auto precharge H L L L
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Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x Op-Code x x x x x x x x x x
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT
ACT/PRE/PALL REF/SELF/MRS
Action Nop Enter row active after tDPL Nop Enter row active after tDPL Nop Enter row active after tDPL Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter precharge after tDPL Nop Enter precharge after tDPL Nop Enter precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC Nop Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRSC Nop Enter idle after tRSC ILLEGAL ILLEGAL ILLEGAL
Notes
x H H H H L L L L x H H H H L L L L x H H L L x H H H L
x H H L L H H L L x H H L L H H L L x H L H L x H H L x
x H L H L H L H L x H L H L H L H L x x x x x x H L x x
8
3 3
3, 8 3 3
L L L L L
Refreshing
H L L L L
Mode register accessing
H L L L L
DESL NOP BST READ/WRIT
ACT/PRE/PALL/ REF/SELF/MRS
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
All entries assume that CKE was active (High level) during the preceding clock cycle. If all banks are idle, and CKE is inactive (Low level), PD4564xxx will enter Power down mode. All input buffers except CKE will be disabled. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. If all banks are idle, and CKE is inactive (Low level), PD4564xxx will enter Self refresh mode. All input buffers except CKE will be disabled. Illegal if tRCD is not satisfied. Illegal if tRAS is not satisfied. Must satisfy burst interrupt condition. Must satisfy bus contention, bus turn around, and/or write recovery requirements. Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied. Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid data
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Data Sheet E0149N10
PD4564441, 4564841, 4564163
4.5 Command Truth Table for CKE
Current State CKE n-1 Self refresh H L L L L L Self refresh recovery H H H H H
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/CS /RAS /CAS /WE n x x H L L L x H L L L H L L L x H L x H L L L L H L L L L x x x x x x x x x H H L x x H H L x H H L x x H x x H L L L x H L L L x x x x x x x x x H L x x x H L x x H L x x x H x x x H L L x x H L L x x x x x x x x x x x x x x x x x x x x x x x H x x x x H L x x x H L x x x x x x x
Address
Action
Notes
x x x x x x x x x x x x x x x x x
INVALID, CLK (n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK (n - 1) would exit power down EXIT power down Idle EXIT power down Idle Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table
H H H H L H H H H L L L L x H H L H H H H H L L L L L x x x H L H L
H H H
Power down
H L L L
All banks idle
H H H H H H H H H H L
x Op-Code
CBR (auto) refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table
x Op-Code x x x x x x
Self refresh Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
1
1
Row active
H L
1
Any state other than listed above
H H L L
2
Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. Remark H = High level, L = Low level, x = High or Low level (Don't care)
Data Sheet E0149N10
19
PD4564441, 4564841, 4564163
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following. (1) (2) To stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well. (4) Two or more CBR (auto) refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
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2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
20
Data Sheet E0149N10
PD4564441, 4564841, 4564163
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A13 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options Wrap type Burst length : A13 through A7 : A3 : A2 through A0
/CAS latency : A6 through A4
Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency www..com /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet E0149N10
21
PD4564441, 4564841, 4564163
7. Mode Register
13 0 13 x 13 12 0 12 x 12 11 0 11 x 11 10 0 10 x 10 9 0 9 1 9 8 0 8 0 8 1 13 x 13 0 12 x 12 0 11 x 11 0 10 x 10 0 9 x 9 0 8 1 8 0 7 1 7 0 7 0 7 1 7 0 6 V 6 5 V 5 LTMODE 4 V 4 3 V 3 WT 2 V 2 1 V 1 BL 0 V 0 Mode Register Set Vender Specific V = Valid x = Don't care 6 6 5 LTMODE 5 4 4 3 WT 3 2 2 1 BL 1 0 Use in future 0 Burst Read and Single Write (for Write Through Cache) 6 5 4 3 2 1 0 JEDEC Standard Test Set (refresh counter test)
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Burst length
Bits2-0 000 001 010 011 100 101 110 111 0 1
WT = 0 1 2 4 8 R R R Full page
WT = 1 1 2 4 8 R R R R
Wrap type
Sequential Interleave
Latency mode
Bits6-4 000 001 010 011 100 101 110 111
/CAS latency R R 2 3 R R R R
Remark R : Reserved
Mode Register Set Timing
CLK CKE /CS /RAS /CAS /WE A0 - A13 Mode Register Set
22
Data Sheet E0149N10
PD4564441, 4564841, 4564163
7.1 Burst Length and Sequence [Burst of Two]
Starting address (column address A0, binary) 0 1 Sequential addressing sequence (decimal) 0, 1 1, 0 Interleave addressing sequence (decimal) 0, 1 1, 0
[Burst of Four]
Starting address (column address A1 - A0, binary) 00 01 10
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Sequential addressing sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2
Interleave addressing sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
11
[Burst of Eight]
Starting address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Sequential addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 1,024 (for 16M x4 device), 512 (for 8M x8 device), and 256 (for 4M x16 device).
Data Sheet E0149N10
23
PD4564441, 4564841, 4564163
8. Address Bits of Bank-Select and Precharge
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A12 0 0 1 1 A13 0 1 0 1 Result Select Bank A "Activate" command Select Bank B "Activate" command Select Bank C "Activate" command Select Bank D "Activate" command
(Activate command)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13 A10 0 0 0 0 1 A12 A13 0 0 1 0 0 1 1 1 x x Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
(Precharge command)
x : Don't care
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disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst)
0 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 x A12 A13 1
(/CAS strobes) A12 0 0 1 1 A13 0 1 0 1 Result enables Read/Write commands for Bank A enables Read/Write commands for Bank B enables Read/Write commands for Bank C enables Read/Write commands for Bank D
24
Data Sheet E0149N10
PD4564441, 4564841, 4564163
9. Precharge
The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. It is depending on the /CAS latency and clock cycle time.
Burst length=4 T0 CLK /CAS latency = 2 Command Read PRE Hi-Z T1 T2 T3 T4 T5 T6 T7 T8
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DQ /CAS latency = 3 Command Read PRE Hi-Z Q1 Q2 Q3 Q4
DQ
Q1
Q2
Q3
Q4
(tRAS must be satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter "tDPL" must be satisfied. The tDPL
(MIN.)
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (MIN.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency 2 3 Read -1 -2 Write +tDPL (MIN.) +tDPL (MIN.)
Data Sheet E0149N10
25
PD4564441, 4564841, 4564163
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode register and whether read or write cycle.
10.1 Read with Auto Precharge www..com
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS latency of 3) the last data word output.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9
/CAS latency = 2 Command READA B Auto precharge starts
Hi-Z DQ QB1 QB2 QB3 QB4
/CAS latency = 3 Command READA B Auto precharge starts
Hi-Z DQ QB1 QB2 QB3 QB4
(tRAS must be satisfied)
Remark READA means Read with Auto precharge
26
Data Sheet E0149N10
PD4564441, 4564841, 4564163
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last data word input to the device.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
/CAS latency = 2 Command DQ WRITA B
Auto precharge starts
Hi-Z DB1 DB2 DB3 DB4 tDPL(MIN.)
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/CAS latency = 3 Command WRITA B Auto precharge starts
Hi-Z DQ DB1 DB2 DB3 DB4 tDPL(MIN.)
(tRAS must be satisfied)
Remark WRITA means Write with Auto Precharge In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency 2 3 Read -1 -2 Write +tDPL (MIN.) +tDPL (MIN.)
Data Sheet E0149N10
27
PD4564441, 4564841, 4564163
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.
Burst length = 4, /CAS latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9
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Read A
Read B
Hi-Z DQ QA1 QB1 QB2 QB3 QB4
1cycle
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction.
Burst length = 4, /CAS latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Write A
Write B
Hi-Z DQ DA1 DB1 DB2 DB3 DB4
1cycle
28
Data Sheet E0149N10
PD4564441, 4564841, 4564163
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
/CAS latency = 2 Command Write A Read B
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Hi-Z DA1 QB1 QB2 QB3 QB4
/CAS latency = 3 Command Write A Read B
Hi-Z DQ DA1 QB1 QB2 QB3 QB4
Data Sheet E0149N10
29
PD4564441, 4564841, 4564163
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data bus must be Hi-Z using DQM before WRITE.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command DQM
Read
Write
Hi-Z DQ D1 1cycle D2 D3 D4
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READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8 T0 CLK /CAS latency = 2 Command DQM Read Write T1 T2 T3 T4 T5 T6 T7 T8 T9
DQ
Q1
Q2
Q3 Hi-Z is necessary
D1
D2
D3
/CAS latency = 3 Command DQM Read Write
DQ
Q1
Q2 Hi-Z is necessary
D1
D2
D3
30
Data Sheet E0149N10
PD4564441, 4564841, 4564163
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command.
12.1 Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to Hi-Z after the /CAS latency from the burst stop command.
Burst length = X T0 CLK T1 T2 T3 T4 T5 T6 T7
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Command
Read
BST
/CAS latency = 2 DQ /CAS latency = 3 DQ Q1 Q2 Q3 Q1 Q2 Q3
Hi-Z
Hi-Z
Remark BST: Burst stop command During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z at the same clock with the burst stop command.
Burst length = X T0 CLK T1 T2 T3 T4 T5 T6 T7
Command
Write
BST
/CAS latency = 2, 3 DQ D1 D2 D3 D4
Hi-Z
Remark BST: Burst stop command
Data Sheet E0149N10
31
PD4564441, 4564841, 4564163
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7
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Read
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
tRP
(tRAS must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
tRP
Q4
(tRAS must be satisfied)
32
Data Sheet E0149N10
PD4564441, 4564841, 4564163
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7
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Write
PRE
ACT
DQM
Hi-Z
DQ
D1
D2
D3
D4
D5
tRP (tRAS must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Write
PRE
ACT
DQM
Hi-Z
DQ
D1
D2
D3
D4
D5
tRP (tRAS must be satisfied)
Data Sheet E0149N10
33
PD4564441, 4564841, 4564163
13. Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on any pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC, VCCQ VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 1 0 to 70 -55 to + 125 Unit V V mA W C C
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Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC, VCCQ VIH VIL TA Condition MIN. 3.0 2.0 -0.3
Note2
TYP. 3.3
MAX. 3.6 VCC+0.3
Note1
Unit V V V C
+0.8 70
0
Notes 1. VIH(MAX.) = VCC + 1.5 V (Pulse width 5 ns) 2. VIL(MIN.) = -1.5 V (Pulse width 5 ns) Pin Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 A0 - A13 CLK, CKE, /CS, /RAS, /CAS, /WE, DQM, UDQM, LDQM DQ0 - DQ15 Condition MIN. 2.5 2.5 TYP. MAX. 4 4 Unit pF
Data input / output capacitance
CI/O
4
6.5
pF
34
Data Sheet E0149N10
PD4564441, 4564841, 4564163
C Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition /CAS latency Operating current ICC1 Burst length = 1, tRC tRC (MIN.), Io = 0 mA, One bank active CL = 3 CL = 2 -A80 -A10 -A10B -A80 -A10 -A10B Precharge standby current in power down mode Precharge standby current in non power down mode
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Grade x4 75 65 60 80 70 70 1 1 20
Maximum x8 80 70 65 85 75 75 1 1 20 x16 90 80 70 115 90 90 1 1 20
Unit
Notes
mA
1
ICC2P ICC2PS ICC2N
CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK (MIN.), Io = 0 mA, All banks active CL = 2 -A80 -A10 -A10B CL = 3 -A80 -A10 -A10B
mA
mA
ICC2NS
6
6
6
Active standby current in power down mode Active standby current in non power down mode
ICC3P ICC3PS ICC3N
5 4 25
5 4 25
5 4 25
mA
mA
ICC3NS
15
15
15
Operating current (Burst mode)
ICC4
90 70 65 105 90 90 130 130 105 135 135 115 1
105 80 70 125 105 105 130 130 105 135 135 115 1
165 130 110 195 165 165 130 130 105 135 135 115 1
mA
2
CBR (auto) refresh current
ICC5
tRC tRC (MIN.)
CL = 2
-A80 -A10 -A10B
mA
3
CL = 3
-A80 -A10 -A10B
Self refresh current
ICC6
CKE 0.2 V
mA
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0149N10
35
PD4564441, 4564841, 4564163
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Input leakage current Symbol II (L) Test condition 0 VI VCCQ, VCCQ = VCC All other pins not under test = 0 V 0 VO VCCQ, DOUT is disabled IO = -4 mA IO = +4 mA MIN. -1.0 -1.5 2.4 0.4 TYP. MAX. +1.0 Unit Note
A A
V V
Output leakage current High level output voltage Low level output voltage
IO (L) VOH VOL
+1.5
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level
www..com (Input rise and fall time) Transition time
Value 2.4 / 0.4 1.4 1 1.4
tCK tCH tCL 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH
Unit V V ns V
Output timing measurement reference level
CLK
Input
Output
36
Data Sheet E0149N10
PD4564441, 4564841, 4564163
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 CLK high level width CLK low level width Data-out hold time /CAS latency = 3 /CAS latency = 2 Data-out low-impedance time Data-out high-impedance time
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-80 MAX.
(125 MHz) (100 MHz)
-10 MIN. 10 13 MAX.
(100 MHz) (77 MHz)
-10B MIN. 10 15 MAX.
(100 MHz) (67 MHz)
Unit
Note
tCK3 tCK2 tAC3 tAC2 tCH tCL tOH3 tOH2 tLZ
8 10
ns ns ns ns ns ns ns ns ns 1 1 1 1
6 6 3 3 3 3 0 3 3 2 1 2 1 2 1 2 2 6 6 3 3 3 3 0 3 3 2 1 2 1 2 1 2 2
6 7 3.5 3.5 3 3 0 6 7 3 3 2.5 1 2.5 1 2.5 1 2.5 2.5
7 8
/CAS latency = 3 /CAS latency = 2
tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS
7 8
ns ns ns ns ns ns ns ns ns ns
Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS, /RAS, /CAS, /WE, DQM) setup time Command (/CS, /RAS, /CAS, /WE, DQM) hold time
tCMH
1
1
1
ns
Note 1. Output load
Z = 50 Output 50 pF
Data Sheet E0149N10
37
PD4564441, 4564841, 4564163
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT (one) to ACT (another) command period Data-in to PRE command period /CAS latency = 3 /CAS latency = 2 Data-in to ACT (REF) command period (Auto precharge)
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-80 MAX. MIN. 70 70
120,000
-10 MAX. MIN. 90 90
120,000
-10B MAX.
Unit
Note
tRC tRC1 tRAS tRP tRCD tRRD tDPL3 tDPL2 tDAL3
70 70 48 20 20 16 8 8 1CLK +20 1CLK +20 2 0.5 30 64
ns ns
120,000
50 20 20 20 10 10 1CLK +20 1CLK +20 2 1
60 30 30 20 10 10 1CLK +30 1CLK +30 2
ns ns ns ns ns ns ns
/CAS latency = 3
/CAS latency = 2
tDAL2
ns
Mode register set cycle time Transition time Refresh time (4,096 refresh cycles)
tRSC tT tREF
CLK 30 64 ns ms
30 64
1
38
Data Sheet E0149N10
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13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3)
T0 tCK T1 T2 T3 T4 T5 T6 T7 T8
;;; ; ;; ;; ;; ;;;; ; ;; ; ;; ;; ;;;; ; ;; ; ;; ;; ;;;; ; ;; ; ;; ;; ;;;; ; ;; ; ;; ; ;; ;; ; ;; ;;; ;; ;; ;; ; ; ;;; ;; ;; ;; ;; ; ; ;; ; ;; ;;; ;; ;; ;; ;;; ;; ;; ;; ;; ; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ; ;; ;;; ; ;; ;; ; ;; ;;;; ; ;;; ; ;; ; ;;
T9 T10 T11 T12 T13 CLK tCH tCL CKE
tCKH
tCKS
tCMS tCMH
/CS
/RAS
/CAS
A12
A10
;; ;; ;; ;;
tAC tAC tAC tAC tHZ tLZ tOH tOH tOH tOH tRP Precharge Command for Bank A Activate Command for Bank A
Data Sheet E0149N10
/WE
A13
PD4564441, 4564841, 4564163
ADD
tAS tAH
DQM DQ
L
Hi-Z
tRCD
tRAS
tRC
Activate Command for Bank A
Read Command for Bank A
39
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A10
; ; ; ; ;
tAC tAC tAC tRCD tLZ tOH tOH tRAS tRRD tRC Read with Auto Precharge Command for Bank C Activate Command for Bank D
40
T0 tCK CLK tCH tCL T1 T2 T3 T4 T5 T6 T7 T8 CKE tCKS tCMS tCMH Auto Precharge Start for Bank C /CS /RAS /CAS
Data Sheet E0149N10
T9
T10
T11
T12
T13
;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;; ;; ; ; ;; ; ;; ; ; ;; ; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ; ; ;; ; ;; ;; ; ;; ; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ;;; ; ;; ; ;;; ;; ; ;;; ;; ; ;;; ;; ; ; ;;;; ;;; ;; ;
tCKH /WE A13 A12
PD4564441, 4564841, 4564163
ADD
tAS tAH
DQM DQ
L
tAC
tHZ
Hi-Z
tOH
tOH
Activate Command for Bank C
Activate Command for Bank C
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13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
T14
T15
T16
T17
T18
T19
T20
T21
; ;;;;; ;;;; ;;;;; ;;;; ;;;;; ;;; ;;;;; ;;;;; ;;;;; ;;; ;;;;; ;; ; ;; ;;;; ;;; ; ;;; ;; ; ;;;; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;;; ; ;; ; ; ;;;; ;;; ; ;
CKE /CS tCKS tCMS tCMH
Auto Precharge Start for Bank C
tCKH
/RAS
/CAS
/WE
A13 A12
A10
;;; ;;;
tDAL tRC tRCD tRAS tRC tDPL Write Command for Bank B
Data Sheet E0149N10
PD4564441, 4564841, 4564163
ADD
tAS tAH
DQM DQ
L tDS tDH Hi-Z tRCD tRRD
tRP
Activate Command for Bank C
Write with Activate Auto Precharge Command Command for Bank B for Bank C
Activate Precharge Command Command for Bank C for Bank B
Activate Command for Bank B
41
PD4564441, 4564841, 4564163
13.3 Relationship between Frequency and Latency
Speed version Clock cycle time [ns] Frequency [MHz] /CAS latency [tRCD] /RAS latency (/CAS latency + [tRCD]) [tRC] [tRC1] [tRAS] [tRRD] [tRP] [tDPL]
www..com [tDAL]
-80 8 125 3 3 6 9 9 6 2 3 1 4 2 10 100 2 2 4 7 7 5 2 2 1 3 2 10 100 3 2 5 7 7 5 2 2 1 3 2
-10 13 77 2 2 4 6 6 4 2 2 1 3 2 10 100 3 3 6 9 9 6 2 3 1 4 2
-10B 15 67 2 2 4 6 6 4 2 2 1 3 2
[tRSC]
42
Data Sheet E0149N10
www..com
T13
;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;;
PD4564441, 4564841, 4564163
T7 T8 T9 T10 T11 T12 T14 T15 T16 T17 T18 T19 T20 T21
2 CLK (MIN.)
T5
tRSC
ADDRESS KEY
Mode Register Set Command DQM ADD /WE A13 A12 A10 Hi-Z DQ Precharge All Banks Command tRP
Data Sheet E0149N10
T0
T1
T2
T3
T4
H
/RAS
/CAS
CKE
CLK
/CS
Activate Command is valid
T6
43
www..com
44
CLK Clock cycle is necessary CKE High level is necessary tRSC /CS /RAS /CAS /WE
Data Sheet E0149N10
2 refresh cycles are necessary
;; ;; ; ;;; ; ;; ;; ; ; ; ;; ; ;; ;; ; ;; ;;; ; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ; ;; ;;; ; ;; ;; ;;; ; ;; ; ;; ; ;; ;; ;; ; ;; ;;; ; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ; ;; ;; ;; ;; ; ;; ;; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ;; ;;; ; ;; ;; ; ;; ;
A13 A12 A10 ADDRESS KEY
PD4564441, 4564841, 4564163
ADD
DQM
High level is necessary Hi-Z
DQ
Precharge All Banks Command is necessary tRP
Mode Register Set Command is necessary
CBR (Auto) Refresh Command is necessary tRC1
CBR (Auto) Refresh Command is necessary tRC1
Activate Command
www..com
Only /CS signal needs to be issued at minimum rate
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
T14
T15
T16
T17
T18
T19
T20
T21
CKE
H
/CS
/RAS
/CAS
Data Sheet E0149N10
/WE
A13
L
A12
L
PD4564441, 4564841, 4564163
A10
RAa
ADD
RAa
CAa
CAb
DQM
L Hi-Z
DQ
QAa1
QAa2 QAa3
QAa4
DAb1
DAb2
DAb3
DAb4
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Precharge Command for Bank A
45
T11
T12
T13
www..com
;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;;; ; ;; ; ;; ;; ;;; ;; ;; ;; ; ;;; ;;; ;; ; ;;; ; ;; ;; ;; ; ;;; ;; ;; ; ;;; ; ;; ;;
PD4564441, 4564841, 4564163
T17 T18 T19 T20 T21 T14 T8 T9 T10 T6 T7 T5 T3 T4 QAa1 QAa2 QAa3 QAa4 T1 /RAS /CAS A13 DQM ADD CKE CLK /WE A12 A10 /CS Hi-Z L
Data Sheet E0149N10
46
DQ
Activate Command for Bank A RAa RAa
T0
Read Command for Bank A CAa
T2
Hi-Z (turn off) at the end of burst
T15
T16
T13
T10
T11
T12
T9
T7
T4
T5
T6
QAa1
QAa2
T8
QAa3
QAa4
www..com
;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;;;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ; ;;;; ;; ;; ;; ;;;; ;; ;;; ;; ; ;; ;; ;;;; ;; ;;
PD4564441, 4564841, 4564163
/RAS /CAS DQM ADD CKE CLK /WE A13 A12 A10 /CS Hi-Z L DQ Activate Command for Bank A RAa RAa Read Command for Bank A CAa Hi-Z (turn off) at the end of burst
Data Sheet E0149N10
T0
T1
T2
T3
T14
T15
T16
T17
T18
T19
T20
T21
47
T12
T13
www..com
48
;; ; ;; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ;; ;; ; ;;; ;; ;; ; ;;; ;; ;; ; ;;; ;; ;; ; ;;; ;; ;; ;;; ;; ;; ;; ; ;; ; ; ;; ;; ;; ;;; ; ;; ;; ;;; ;; ;; ;;; ; ;; ;; ; ;; ;; ;;; ; ;; ; ; ;
PD4564441, 4564841, 4564163
T14 T15 T16 T17 T18 T19 T20 T21 T8 T9 T10 T11 T5 T6 T7 T3 T4 DAa2 DAa3 DAa4 T1 /RAS /CAS DQM ADD CKE CLK /WE A13 A12 A10 /CS
Data Sheet E0149N10
DQ
Hi-Z
T0
L
Activate Command for Bank A RAa RAa
Write Command for Bank A DAa1 CAa
T2
www..com
T13 DAa4
;; ; ;;; ; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ; ;;; ;; ; ;; ;; ;; ; ;;; ;; ; ;; ;; ;; ; ;;; ;; ; ;; ;; ;; ;;; ;;; ;; ; ;; ;; ;; ; ;;; ;; ; ;; ;; ;; ;; ;; ;;; ;; ;; ;;; ;; ; ;; ;;; ;; ;; ; ;;; ;; ; ;; ;; ;; ; ;;; ;; ;; ; ;; ;; ;;; ;; ; ;;; ;; ; ;;; ;; ;; ;;; ;;; ;; ;; ;;
PD4564441, 4564841, 4564163
T9 T10 T11 T12 T14 T15 T16 T17 T18 T19 T20 T21 T6 T7 T8 T4 T5 DAa2 DAa3 T1 T2 /RAS /CAS DQM ADD CKE CLK /WE A13 A12 A10 /CS Hi-Z T0 L DQ Activate Command for Bank A RAa RAa Write Command for Bank A DAa1 CAa T3
Data Sheet E0149N10
49
T10
T11
T12
T13
www..com
;; ;; ; ;; ; ;; ;; ;;; ; ; ;; ;; ;;; ; ; ;; ;; ;;; ; ; ;; ;; ;;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;; ;; ; ; ;;; ;; ;; ; ; ;;; ;;; ; ;; ; ; ;;; ;; ; ;; ;; ; ;;; ; ; ;; ; ; ;;; ;; ;;; ; ; ;; ; ;;; ;;; ; ; ;; ; ;;; ;;; ;; ;; ; ;;; ;;; ;; ;; ; ; ;; ;;; ;; ;; ; ;
PD4564441, 4564841, 4564163
tCKSP VALID QAa1 QAa2 QAa3 QAa4 tCKSP /RAS /CAS DQM ADD CKE CLK /WE A13 A12 A10 /CS Hi-Z L
Data Sheet E0149N10
T15
T16
T17
T18
T19
T20
T21
T6
T7
T8
T9
T14
T1
T2
T3
T4
50
DQ
Activate Command for Bank A RAa RAa
T0
Read Command for Bank A CAa
T5
Precharge Command for Bank A
Tn + 3 Tn + 4 Tn + 5 Tn + 6
Tn
Tn + 1 Tn + 2
T2
T3
T4
T5
/RAS
/CAS
DQM
ADD
CKE
CLK
/WE
A13
A12
A10
/CS
DQ
Precharge Command (if necessary)
T1
Hi-Z
T0
H
L
Data Sheet E0149N10
tRP
tRC1
T6
tRC1
www..com
;; ;;; ; ;; ;; ;; ;;; ;; ;; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;;; ;; ;; ;; ; ; ;; ;; ; ;;; ;; ;; ;; ; ;; ;; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;;; ; ;; ;; ; ;; ;; ; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;;; ;; ;; ;; ; ; ;; ;; ;; ; ;; ;; ;;; ;; ; ;; ; ; ; ;; ;; ; ;;; ;; ;; ;; ;; ;; ;; ;; ;;; ;; ;;
PD4564441, 4564841, 4564163
Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Q1 Tm Activate Command Read Command
51
www..com
Tm + 1
;; ;; ; ;;; ; ;; ;; ; ;; ;; ; ;; ; ;; ; ; ; ;;; ; ; ;; ;; ; ;; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ;; ;; ;;; ; ;; ;; ; ;;; ; ;; ;; ;; ;;; ; ;; ; ;; ;; ;; ; ;; ;;; ; ;; ;; ;;; ; ;; ;; ;; ;; ; ;;; ; ;; ;; ;;;; ; ;; ; ;; ;; ;;;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;;; ; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ; ;; ;
PD4564441, 4564841, 4564163
Activate Command Next Clock Enable (or Activate Command) Next Clock Enable Precharge Command (if necessary) tRP DQM ADD /WE A13 A12 A10 L Hi-Z DQ tRC1 tRC1 /RAS /CAS CKE CLK /CS
Data Sheet E0149N10
52
T0
T1
T2
T3
T4
Tn
Tn + 1 Tn + 2
Tm
Tk
Tk + 1 Tk + 2 Tk + 3 Tk + 4
www..com
T13 QAc3 Precharge Command for Bank A Activate Command for Bank A RAa RAa /RAS /CAS DQM ADD /WE A13 A12 A10 /CS L Hi-Z DQ Read Command for Bank A CAa Read Command for Bank A CAb QAa1 QAa2 Read Command for Bank A QAa3 QAa4
;;; ; ; ;;;; ; ; ;; ;; ;;;; ; ; ;; ;; ;;;; ; ;; ; ; ; ; ;; ;;;; ; ; ;; ;; ; ; ; ;;;; ; ;; ;; ; ; ; ; ; ;; ;; ;;;; ; ; ;; ;; ;; ;; ;;;; ; ; ;; ;; ; ; ;;;; ; ; ;; ;; ;;;; ; ;; ;; ; ;; ;; ;; ;;;; ; ;;; ; ;; ;; ;; ; ;; ;; ;;;; ; ;;; ;; ;; ; ;; ;;; ; ;; ;; ;; ;;;; ; ; ;; ;; ; ;; ; ;;;; ; ;; ;; ;; ; ;; ; ;;;; ; ;; ;; ;; ; ;; ;;;; ; ;; ;; ;;; ;; ; ;; ;; ;;;; ; ;; ;; ; ;; ;
PD4564441, 4564841, 4564163
QAd3 QAd1 QAd2 T17 T18 T19 T20 T21 T15 T16 T14 T12 T11 T10 T0 T1 T2 T3 T4 T5 T6 T7 T8 CKE CLK H CAc QAb1 T9 QAb2 QAc1 QAc2 QAc4 Activate Command for Bank A RAd RAd Read Command for Bank A CAd
Data Sheet E0149N10
53
www..com
54
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE H /CS /RAS /CAS
Data Sheet E0149N10
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ; ;; ;;;; ; ;; ;; ; ;; ;; ;;;; ; ; ;;;; ; ;; ;; ;; ;;;; ; ;; ;; ;;;; ; ;; ;; ;; ;;;; ; ;; ; ;; ;; ;; ;; ;;;; ; ;; ;;;; ; ;; ; ;; ;; ;;;; ; ; ;;; ;; ;; ;;;; ; ; ;;; ;; ;; ; ;;;; ; ; ;;; ;; ;; ; ; ; ;;;; ; ; ;; ; ; ; ;;;; ; ;;; ;; ;; ; ;; ; ; ; ; ;;;; ; ; ;; ;; ; ; ;;;; ; ;; ;; ; ;;;; ; ;; ; ; ;; ; ;;;; ; ;; ; ;
/WE A13 A12
PD4564441, 4564841, 4564163
A10
RAa
RAa
ADD
RAa
CAa
CAb
CAc
RAa
CAa
DQM
L
Hi-Z DQ
QAa1
QAa2
QAa3
QAa4
QAb1
QAb2
QAc1
QAc2
QAc3
QAc4
Activate Command for Bank A
Read Command for Bank A
Read Command for Bank A
Read Command for Bank A
Precharge Command for Bank A
Activate Command for Bank A
Read Command for Bank A
www..com T13 Precharge Command for Bank D Activate Command for Bank D RDa RDa /RAS /CAS DQM ADD /WE A13 A12 A10 /CS DQ Hi-Z L
Data Sheet E0149N10
;; ; ;; ;;; ; ;; ;; ;; ;;;; ; ;; ;; ;; ;;;; ; ;; ;; ; ; ;; ;;;; ; ;;; ;; ;; ;; ;;;; ; ;; ; ;; ; ;; ;; ;;; ;; ;; ;;;; ; ;; ;; ;; ;; ;;;; ; ;; ;; ;; ;; ; ;;;; ; ;; ;; ;; ; ;;;; ; ;; ;; ; ;;; ;; ; ;;;; ; ;;; ;;; ;; ;; ; ; ; ; ; ;;;; ; ;;; ; ;; ;; ; ; ;; ; ; ;;;; ; ;; ;; ; ; ;; ; ; ;;;; ; ;; ;; ; ;; ; ; ;;;; ; ;; ;; ; ;; ; ;;;; ; ;;; ;; ;; ;; ; ;; ; ;;;; ; ;; ;; ;; ; ;;;; ; ;; ;; ; ;; ;
PD4564441, 4564841, 4564163
T20 T21 T19 T18 T17 DDd2 DDd3 DDd4 T15 T16 T12 T14 T11 T10 T9 DDc2 DDc3 DDc4 DDb2 T5 T4 T3 DDa2 DDa3 DDa4 T0 T1 CKE CLK H Write Command for Bank D DDa1 CDa T2 Write Command for Bank D DDb1 CDb T6 T7 Write Command for Bank D DDc1 T8 CDc Activate Command for Bank D RDd RDd Write Command for Bank D DDd1 CDd
55
www..com
56
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CKE H /CS /RAS /CAS
Data Sheet E0149N10
T14
T15
T16
T17
T18
T19
T20
T21
;;; ; ; ;;;; ; ;; ; ;; ;; ; ;; ;; ;;;; ; ;; ;;;; ; ;; ; ;; ;; ; ;; ;;;; ; ;; ;; ;;;; ; ;; ;; ;; ;;;; ; ;; ;; ;; ;;;; ; ;; ; ;;;; ; ;; ; ;; ;; ;; ; ;; ;;;; ; ; ;;; ;;; ;; ;; ;; ;;;; ; ; ;;; ;; ;; ; ; ; ;;;; ; ; ;; ; ; ; ;;;; ; ; ;; ;; ; ; ; ;;;; ; ;; ; ; ; ;; ;;;; ; ;; ;; ; ; ;;;; ; ; ;;; ;; ;; ;; ;;;; ; ;; ; ; ;
/WE A13 A12
PD4564441, 4564841, 4564163
A10
RDa
RDd
ADD
RDa
CDa
CDb
CDc
RDd
CDd
DQM
L
DQ
Hi-Z
DDa1
DDa2
DDa3
DDa4
DDb1
DDb2
DDc1
DDc2
DDc3
DDc4
DDd1 DDd2
Activate Command for Bank D
Write Command for Bank D
Write Command for Bank D
Write Command for Bank D
Precharge Command for Bank D
Activate Command for Bank D
Write Command for Bank D
www..com
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ; ; ; ;; ;; ;; ;; ; ;; ;; ;; ; ; ;; ;; ;; ; ; ;; ;; ; ;; ; ; ; ; ;; ;; ;; ;; ;; ;;;; ; ; ;; ; ;; ; ; ; ; ; ;; ;; ;; ; ; ; ;; ; ; ;; ; ; ; ;; ;; ;; ;; ; ;; ;; ;; ; ; ;; ;; ;; ; ; ;; ;; ;; ; ; ; ; ; ; ; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ;;
CKE H /CS /RAS /CAS
Data Sheet E0149N10
/WE
A13
A12
PD4564441, 4564841, 4564163
A10
RDa
RBa
RDb
ADD
RDa
CDa
RBa
CBa
RDb
CDb
DQM
L
DQ
Hi-Z
QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1
QBa2 QBa3 QBa4
QBa5 QBa6 QBa7
QBa8
Activate Command for Bank D
Read Command for Bank D
Activate Command for Bank B
Read Command for Bank B Precharge Command for Bank D
Activate Command for Bank D
Read Command for Bank D
57
www..com
58
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK CKE H /CS /RAS /CAS /WE
Data Sheet E0149N10
T14
T15
T16
T17
T18
T19
T20
T21
;;; ; ;; ;; ;;;; ; ;; ;;;; ; ;; ;; ;;;;;; ;; ;;;; ; ; ;; ;;;;;; ; ;;; ;;;; ;;;;;; ;; ;;;; ; ;; ;;;;;; ;; ;;;; ;;;;;; ;;;;; ; ;; ;; ;;; ;; ;; ;;;;;; ;;; ;;;;; ;; ;; ;; ;;;; ; ;;; ;; ;;;;;; ; ; ;;;; ; ;; ;;;;;; ; ;; ;; ;;; ;;;; ;;;;;; ;;; ;;;; ;;;;;; ;; ;;;; ;;;;;; ;;;;; ;; ;; ;; ;; ;; ;;;;;; ;;;; ;;;; ;; ;; ;;;;;; ;;; ;;;; ;;;;; ;; ;; ;;; ;;;;;; ;;;; ;;;; ;;;
A13 A12 A10 RBa RAa RBb
PD4564441, 4564841, 4564163
ADD
RBa
CBa
RAa
CAa
RBb
CBb
DQM
L
DQ
Hi-Z
QBa1 QBa2
QBa3 QBa4
QBa5 QBa6
QBa7 QBa8
QAa1
QAa2 QAa3 QAa4
QAa5 QAa6 QAa7
Activate Command for Bank B
Read Command for Bank B
Activate Command for Bank A
Read Command for Bank A
Precharge Command for Bank B
Activate Command for Bank B
Read Command for Bank B
Precharge Command for Bank A
www..com
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ;;; ;; ;; ;; ; ; ;; ;; ;;; ;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ; ;;; ;; ;;; ; ; ;; ;; ; ;; ;;; ;; ;; ;; ;; ; ;; ;;; ;; ; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ; ;; ;; ;; ;; ; ;;;; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ;; ;;;; ;; ; ;; ; ;; ;; ; ;;;; ;;; ;; ;; ;; ; ;;
CKE H /CS /RAS /CAS /WE A13 A12
Data Sheet E0149N10
PD4564441, 4564841, 4564163
A10
RAa
RDa
RAb
ADD
RAa
CAa
RDa
CDa
RAb
CAb
DQM
L
DQ
Hi-Z
DAa1
DAa2
DAa3
DAa4
DAa5
DAa6
DAa7
DAa8
DDa1 DDa2
DDa3 DDa4
DDa5
DDa6 DDa7 DDa8
DAb1
DAb2
DAb3
Activate Command for Bank A
Write Command for Bank A
Activate Command for Bank D
Write Command for Bank D Precharge Command for Bank A
Activate Command for Bank A
Write Command for Bank A Precharge Command for Bank D
59
www..com
60
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CKE H /CS /RAS /CAS
Data Sheet E0149N10
T14
T15
T16
T17
T18
T19
T20
T21
; ; ;; ; ;; ;;; ;;; ;;;;; ; ;;;;; ;;;; ;; ;;; ;;;;;; ;; ;; ;; ; ;; ;;;; ;; ; ; ;; ;; ;; ;; ; ;; ;; ;; ;;;; ;; ;;; ;; ;; ; ; ;;; ; ;;; ;;; ;;;;;; ;;; ; ;;;; ;; ; ;;;;; ;;;; ;; ;;; ;;;;; ;; ;; ;; ;; ;;; ; ; ;;; ; ;;; ; ;; ; ;; ; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ; ; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ;;;; ;;; ;; ;; ;; ; ; ;;;; ;; ; ;; ; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;; ;;;; ;; ; ;; ;; ;;
/WE A13 A12 A10 RAa RDa RAb
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RDa
CDa
RAb
CAb
DQM
L
DQ
Hi-Z
DAa1
DAa2
DAa3
DAa4
DAa5
DAa6
DAa7
DAa8
DDa1 DDa2
DDa3
DDa4 DDa5 DDa6
DDa7 DDa8 DAb1
DAb2
Activate Command for Bank A
Write Command for Bank A
Activate Command for Bank D
Write Command for Bank D
Precharge Command for Bank A
Activate Command for Bank A
Write Command for Bank A
Precharge Command for Bank D
www..com
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CKE
H
;; ;; ; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ; ;; ;; ; ;; ;; ;;; ;; ; ;; ;;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ; ;; ;; ; ;;; ; ;; ;; ;;; ; ; ;; ;; ;; ; ; ;; ;; ;;; ; ;; ;; ; ;; ;
/CS /RAS /CAS /WE A13 A12
Data Sheet E0149N10
PD4564441, 4564841, 4564163
A10
RAa
ADD
RAa
CAa
CAb
CAc
Write Latency = 0
DQM
L
Word Masking
DQ
Hi-Z
QAa1
QAa2
QAa3
QAa4
DAb1
DAb2
DAb4
QAc1
QAc2
QAc4
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Read Command for Bank A
61
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
www..com
62
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK CKE H /CS /RAS /CAS
Data Sheet E0149N10
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ; ; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ; ;; ;; ; ;; ;; ;;;; ; ;;; ;; ; ;; ;; ;;;; ; ; ;; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ; ;; ; ;; ; ;; ;; ;; ; ;; ;;;; ; ;; ;; ; ;; ;;;; ; ; ;; ;; ;; ;;; ;; ;; ;;;; ; ;; ;; ;; ; ; ;; ;
/WE A13 A12
PD4564441, 4564841, 4564163
A10
RAa
ADD
RAa
CAa
CAb
CAc
Write Latency = 0
DQM
L
Word Masking DQ Hi-Z QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Read Command for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
www..com
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CKE
H
/CS
;; ;; ;; ;; ;; ; ;; ; ;; ;; ; ; ; ; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ;; ;; ; ;;; ;; ;; ;; ;; ; ;; ;; ;; ; ; ; ;; ; ;; ; ;; ;; ;; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;;
/RAS /CAS
Data Sheet E0149N10
/WE
A13
A12
PD4564441, 4564841, 4564163
A10
RAa
RDa
ADD
RAa
CAa
RDa
CDa
CDb
CDc
CAb
CDd
DQM
L Hi-Z
DQ
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Dd1
Dd2
Dd3
Dd4
Activate Command for Bank A
Read Command for Bank A
Activate Command for bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank A
Read Command for Bank D Precharge Command for Bank A
Precharge Command for Bank D
63
www..com
64
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CKE H /CS /RAS /CAS
Data Sheet E0149N10
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ;; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ;;; ; ;; ;; ; ;; ; ;; ;; ;;;; ;; ; ;; ; ;; ;; ;; ;; ;;;; ;; ; ;; ;; ;; ;; ; ;; ;; ; ;; ; ; ;; ;;; ; ; ; ;; ;; ;; ; ;; ; ;; ;;; ;; ;; ; ;; ; ; ;; ; ;; ; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;;; ; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;;
/WE A13 A12
PD4564441, 4564841, 4564163
A10
RAa
RDa
ADD
RAa
CAa
RDa
CDa
CDb
CDc
CAb
DQM
L
DQ
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Ab3
Ab4
Activate Command for Bank A
Read Command for Bank A Activate Command for Bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A
www..com
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;; ; ;; ;; ; ;;;; ; ;; ; ; ;;;; ; ; ;; ; ;;;; ; ; ; ;;;; ; ; ;;;; ; ;; ;;;; ; ;;; ;;; ;; ;; ; ;; ;;;; ; ;; ; ;;; ; ;; ;;;; ; ;;; ;;; ;; ;; ; ;; ;;;; ; ;;; ;; ; ;; ; ;;;; ; ; ;;; ;; ;; ; ;;;; ; ;; ; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;; ;; ; ;;;; ; ; ;; ; ; ;;;; ; ; ;;;; ; ;; ; ; ;;;; ; ;; ; ; ;
CKE H /CS /RAS /CAS
Data Sheet E0149N10
/WE
A13
A12
PD4564441, 4564841, 4564163
A10
RAa
RBa
ADD
RAa
CAa
RBa
CBa
CBb
CBc
CAb
CBd
DQM
L
Hi-Z
DQ
Aa1
Aa2
Aa3
Aa4
Ba1
Ba2
Bb1
Bb2
Bc1
Bc2
Ab1
Ab2
Bd1
Bd2
Bd3
Bd4
Activate Command for Bank A
Write Command for Bank A
Activate Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank A
Write Command for Bank B
Precharge Command for Bank A Precharge Command for Bank B
65
www..com
A13
A12
; ;
CBd Ab2 Bd1 Bd2 Bd3 Bd4 Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B
66
Data Sheet E0149N10
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ;;; ;; ;;;; ; ;;;; ;;; ;; ;; ; ;; ;; ;; ; ;; ;; ; ;; ;;; ;; ;; ;;; ;; ;; ;; ;;;; ;;; ;;;; ;;; ; ;; ;; ;; ;;; ; ;; ;; ;;;; ;;; ;; ;;; ;; ;; ;;;; ;;; ;; ; ; ; ;; ;; ; ; ; ;;;; ;; ; ;; ;;; ;; ; ;;; ; ; ;; ; ;; ;;;; ;; ;; ; ;;; ;; ;;; ;;;; ;; ;;; ;; ;;;; ;; ;;; ;; ;;;; ;;; ; ;; ;; ;;; ;; ;;; ;; ;; ;;;; ;; ; ; ;; ;; ;;; ;; ; ;; ;; ;;;; ;; ; ; ;; ;;
CKE H /CS /RAS /CAS /WE
PD4564441, 4564841, 4564163
A10
RAa
RBa
ADD
RAa
CAa
RBa
CBa
CBb
CBc
CAb
DQM
L
DQ
Hi-Z
Aa1
Aa2
Aa3
Aa4
Ba1
Ba2
Bb1
Bb2
Bc1
Bc2
Ab1
Activate Command for Bank A
Write Command for Bank A Activate Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank A
www..com
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;; ;; ;; ;;; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ; ; ;; ;; ;;;; ;; ;; ; ; ;; ;; ;; ;; ;; ;;;; ;; ; ; ;; ;; ; ; ; ;;;; ;; ; ; ;; ; ; ;; ; ;; ;; ; ;;; ; ; ; ;; ; ;; ; ;; ;; ;;; ; ;; ;; ;;; ;; ; ; ;; ;; ;; ;; ;; ; ;; ;;; ; ;; ; ;; ;; ;;;; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ; ; ;;; ; ;; ; ;; ; ;; ;; ;; ; ;;; ; ;; ; ; ;; ;; ;; ; ;; ; ;; ;;; ; ;; ; ;; ;; ;; ;;;; ;; ;; ; ;;; ;; ;; ; ;; ;; ;;;; ;; ; ;; ;;;; ;;; ;; ;; ;; ;
CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RDa RDb RAc
Data Sheet E0149N10
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
L
DQ
Hi-Z
Activate Command for Bank A
Read Command for Bank A
Activate Command for Bank D
Read with Auto Precharge Command for Bank D
Read with Auto Precharge Command for Bank A Auto Precharge Start for Bank D
Activate Command for Bank D
Activate Command Read with Read with for Bank A Auto Precharge Auto Precharge Command Command for Bank A for Bank D Auto Precharge Auto Precharge Start for Bank A Start for Bank D
67
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68
Data Sheet E0149N10
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
; ; ;;; ; ;; ;; ;;;; ; ;; ;; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ;; ; ;;;; ; ;; ; ;; ;; ; ;;;; ; ;; ;; ;;;; ; ;; ;; ;; ; ;; ;; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ;;;; ; ;; ;; ;;;; ; ; ;; ;; ;;;; ; ;; ; ;; ;; ;;;; ; ; ;; ;; ;;;; ; ;; ;; ;; ; ;
CLK CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RDa RDb
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
DQM
L
DQ
Hi-Z
Activate Command for Bank A
Activate Command for Bank D Read Command for Bank A Read with Auto Precharge Command for Bank D
Read with Auto Precharge Command for Bank A Auto Precharge Start for Bank D
Activate Command for Bank D
Read with Auto Precharge Command for Bank D Auto Precharge Start for Bank A
www..com
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;; ;; ; ;; ;;;; ;; ; ; ;; ;; ;;;; ;; ; ; ;; ;; ;;;; ;; ; ; ;; ;; ;;;; ;; ; ; ;; ;; ;; ;;; ; ;; ;;;; ; ;; ; ;; ; ; ;; ;;; ; ; ;; ; ; ; ;; ;; ; ;; ;;; ; ;; ; ; ;; ;; ;; ; ;;;; ;; ; ; ;; ;; ;; ; ;; ; ;;; ; ;; ;; ;; ;;;; ;;; ;; ;; ;;;; ;; ; ; ;; ;; ;;;; ; ;; ;; ;; ;; ; ;; ;; ;; ; ; ;; ;;; ;; ;; ;; ; ;; ;; ;; ;;;; ;; ; ; ;; ;; ;; ;; ;;;; ;; ; ;;; ;; ;; ; ;;;; ;;; ;; ;; ;; ;; ; ;;; ;; ;; ;;;; ;;; ;; ;; ; ;; ;
CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RDa RDb RAc
Data Sheet E0149N10
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
L
DQ
Hi-Z
Activate Command for Bank A Write Command for Bank A
Activate Command for Bank D Write with Auto Precharge Command for Bank D Write with Auto Precharge Command for Bank A
Activate Command for Bank D
Activate Command for Bank A
Write with Write with Auto Precharge Auto Precharge Command Command for Bank D for Bank A Auto Precharge Auto Precharge Auto Precharge Start for Bank D Start for Bank A Start for Bank D
69
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70
Data Sheet E0149N10
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;; ;; ; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;; ; ;;; ; ;; ;;;; ;; ; ;; ;; ;;;; ;; ;; ; ;; ; ; ;; ;; ;;;; ;; ; ;; ;; ;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;; ; ;;; ;; ;; ;;;; ; ;;; ;; ;; ; ;;;; ;; ; ;; ;; ;;;; ;; ; ;;; ;; ;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ; ;; ;; ;; ; ;;; ;; ;; ;;;; ;; ; ;; ;;
CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RDa RDb
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
DQM
L Hi-Z
DQ
Activate Command for Bank A
Activate Command for Bank D Write Command for Bank A Write with Auto Precharge Command for Bank D
Write with Auto Precharge Command for Bank A
Activate Command for bank D
Auto Precharge Start for Bank D
Auto Precharge Start for Bank A
Write with Auto Precharge Command for Bank D
www..com
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
; ;;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;; ; ; ;; ; ;;;; ; ;; ;; ; ;;;; ; ; ;; ;;;; ; ; ;; ;;;; ; ; ;; ;;;; ; ;; ;; ;; ;; ;;;; ; ;;; ; ;; ;; ;;;; ; ;; ; ;;;; ; ; ;; ;;;; ; ;; ;; ;; ;; ;; ;;;; ; ;; ;; ; ; ; ;;;; ; ;; ;; ; ; ;;;; ; ; ;;; ;; ;; ;; ; ; ;;;; ; ; ;;;; ; ;; ; ; ;
CKE H /CS /RAS /CAS /WE A13 A12
Data Sheet E0149N10
PD4564441, 4564841, 4564163
A10
RAa
RDa
RDb
ADD
RAa
CAa
RDa
CDa
RDb
DQM
L
DQ
Hi-Z
Aa
Aa+1
Aa+2
Aa-2
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Da+6
Activate Command for Bank A
Read Command for Bank A
Activate Command for Bank D
Read Command for Bank D
Burst Stop Command
Precharge Command for Bank D
Activate Command for Bank D
71
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72
Data Sheet E0149N10
Full Page Read Cycle (2/2) (/CAS latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12
;; ; ;;; ;; ; ; ;;;; ;; ; ;;;; ;; ;;;; ;; ; ;; ;;;; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ;; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ;; ;;;; ;; ;; ; ; ;;;; ;; ; ; ;;;; ;;; ;;
CKE H /CS /RAS /CAS /WE A13 A12
PD4564441, 4564841, 4564163
A10
RAa
RDa
RDb
ADD
RAa
CAa
RDa
CDa
RDb
DQM
L Hi-Z
DQ
Aa
Aa+1
Aa-3
Aa-2
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Activate Command for Bank A
Read Command for Bank A
Activate Command for Bank D
Read Command for Bank D
Burst Stop Command
Precharge Command for Bank D
Activate Command for Bank D
www..com
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
T0 CLK T1 T2 T3 T4 T5 Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 Tn + 14 Tn + 15
;;; ; ;; ;;; ;;; ; ;; ;; ;;; ; ;;; ; ;; ;; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;;;; ; ;; ;;; ;; ;;;; ; ;; ;;; ;; ;;;; ; ; ; ;; ;;; ;; ;;; ;; ; ; ; ;; ;;;; ; ;; ;;; ;; ;;;; ; ;; ;; ; ;;; ;; ;;; ;; ;; ; ;;;;; ;; ; ;;;; ;;; ;; ;; ;; ;;;; ;;; ;; ;; ;;
CKE H /CS /RAS /CAS /WE A13 A12
Data Sheet E0149N10
PD4564441, 4564841, 4564163
A10
RAa
RDa
RDb
ADD
RAa
CAa
RDa
CDa
RDb
DQM
L
DQ
Hi-Z
Aa
Aa+1
Aa+2
Aa-2 Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Activate Command for Bank A
Write Command for Bank A
Activate Command for Bank D
Write Command for Bank D Burst Stop Command
Precharge Command for Bank D Activate Command for Bank D
73
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74
Data Sheet E0149N10
Full Page Write Cycle (2/2) (/CAS Latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
;;; ;; ;;; ; ;; ;; ;; ; ; ; ;;; ; ;; ; ; ;;; ; ; ; ;; ; ; ;;;; ;; ; ;; ;;;; ;; ; ; ;;;; ;; ; ; ;;;; ;; ; ; ;;;; ;; ;; ; ; ;; ; ;;;; ;;; ;; ;;;; ;; ; ; ;;;; ;; ; ; ;;;; ;; ; ; ;;;; ;; ;; ; ;; ; ; ;;;; ;; ; ;; ;;; ; ;; ; ; ;; ;; ; ; ;;; ; ;; ; ;;
CKE H /CS /RAS /CAS /WE A13 A12 A10
PD4564441, 4564841, 4564163
RAa
RDa
RDb
ADD
RAa
CAa
RDa
CDa
RDb
DQM
L Hi-Z
DQ
Aa
Aa+1
Aa+2
Aa+3
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Activate Command for Bank A
Write Command for Bank A
Activate Command for Bank D
Write Command for Bank D Burst Stop Command Burst is not completed in the Full Page Mode
Precharge Command for Bank D
Activate Command for Bank D
www..com
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CKE /CS
;; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;;;; ;;; ; ; ;;;; ;;; ; ; ;;;; ;;; ; ; ;;;; ;;; ; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;; ; ;;;; ;;; ; ; ;;;; ;;; ; ; ;;;; ;;; ;;;; ;;; ;; ; ; ;;;; ;;; ; ;; ; ; ;;;; ;;; ; ;; ; ;
/RAS /CAS /WE A13 A12 A10
Data Sheet E0149N10
PD4564441, 4564841, 4564163
ADD
LDQM
UDQM
DQ (lower)
DQ (upper)
Activate Command for Bank D
Read Command for Bank D
Upper Byte not Read
Lower Byte Upper Byte Lower Byte not Write not Write not Write
75
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76
Data Sheet E0149N10
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CKE /CS
H
;; ; ; ;; ;; ;; ;; ; ;;; ; ; ;;; ; ;; ; ;; ;;; ; ; ;; ; ;;; ; ; ;; ; ;;; ; ;; ; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ;;; ; ;; ;; ;; ; ;;; ; ;; ;; ; ;;; ; ; ;; ; ;;; ; ; ;; ; ;;; ; ; ;; ; ;;; ; ;; ; ;;; ; ;; ; ;;; ; ;; ;;; ; ;; ; ;;; ; ;; ; ;; ;;
/RAS /CAS /WE A13 A12 A10
PD4564441, 4564841, 4564163
ADD
DQM DQ
Hi-Z
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
D2
Activate Command for Bank D
Read Command for Bank D
Single Write Command for Bank D
Single Write Command for Bank D
Read Command for Bank D
Single Write Command for Bank D
www..com
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ; ;; ; ; ;;; ; ;; ; ; ; ;;; ; ;; ;; ;; ; ;;; ; ;; ; ;; ;; ;; ;; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;; ;; ;; ; ; ;;; ; ; ;; ; ;; ; ; ;;; ; ;; ; ; ;; ; ;;; ; ;; ; ;; ;;; ; ;;; ; ;; ; ;;; ; ;; ; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;;
CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RDa
Data Sheet E0149N10
PD4564441, 4564841, 4564163
ADD
RAa
RDa
CAa
CDa
CAb
CDb
CAc
CDc
DQM
L Hi-Z
DQ
QAa1 QDa1
QAb1 QAb2
QDb1 QDb2
QAc1
QAc2
QAc3
QDc1
QDc2
QDc3
Activate Command for Bank A
Activate Command for Bank D Read Command for Bank A
Read Command for Bank A
Read Command for Bank D
Read Command for Bank A
Read Command for Bank D
Precharge Command for Bank D (PRE Termination of Burst)
Read Command for Bank D
77
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78
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE H /CS /RAS /CAS
Data Sheet E0149N10
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;;;; ; ;; ; ;; ; ;; ; ;;;; ; ;;; ; ; ;;;; ; ;; ; ;;;; ; ; ;;; ;; ; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ; ;
/WE A13 A12 A10 RAa RDa
PD4564441, 4564841, 4564163
ADD
RAa
RDa
CAa
CDa
CAb
CDb
CAc
CDc
DQM
L
DQ
Hi-Z
DAa1 DDa1
DAb1
DAb2
DDb1
DDb2
DAc1
DAc2
DAc3
DDc1
DDc2
DDc3
DDc4
Activate Command for Bank A
Activate Command for Bank D Write Command for Bank A
Write Command for Bank A
Write Command for Bank D
Write Command for Bank A
Write Command for Bank D
Precharge Command for Bank D (PRE Termination of Burst)
Write Command for Bank D
www..com
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;; ; ; ;;; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ;; ;; ; ; ;;; ; ;; ; ;; ;;; ; ; ;; ; ; ; ;;; ; ;; ; ; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;;; ; ;; ; ; ;; ; ;; ; ; ;;; ; ;; ; ;;
CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RAb RAc
Data Sheet E0149N10
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RAb
CAb
RAc
DQM
L Hi-Z
Write Masking DAa1 DAa2 DAa3 DAa4 DAa5 QAb1 QAb2 QAb3 QAb4 QAb5 Hi-Z
DQ
Activate Command for Bank A
Write Command for Bank A PRE Termination of Burst tRCD tRAS Precharge Command for Bank A tDPL tRP Activate Command for Bank A
Read Command for Bank A PRE Termination of Burst tRAS Precharge Command for Bank A
Activate Command for Bank A
79
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80
Data Sheet E0149N10
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
; ;; ;;; ; ;; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;; ;; ;; ;; ; ;; ; ;; ;; ;;;; ; ;; ;; ;; ; ;;;; ; ;; ;; ;; ;;;; ; ;; ;; ;;;; ; ; ;; ; ;; ;;;; ; ;; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;; ;; ;; ;; ;; ;;;; ; ;; ;; ;; ; ;;;; ; ;; ;; ;; ;;;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;;; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;; ;; ; ;; ;
CLK CKE H /CS /RAS /CAS /WE A13 A12 A10 RAa RAb RAc
PD4564441, 4564841, 4564163
ADD
RAa
CAa
RAb
CAb
RAc
DQM
L
Write Masking DAa5
Hi-Z DQ
DAa1
DAa2
DAa3
DAa4
Hi-Z
QAb1 QAb2
QAb3 QAb4
Activate Command for Bank A
Write Command for Bank A PRE Termination of Burst tRCD tRAS Precharge Command for Bank A tDPL tRP Activate Command for Bank A
Read Command for Bank A PRE Termination of Burst tRAS Precharge Command for Bank A
Activate Command for Bank A
PD4564441, 4564841, 4564163
14. Package Drawing
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
54 28
detail of lead end F
P E 1 www..com 27 A H G I S L C D M
M
J
N
S
B
K
NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold fiash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 22.220.05 0.91 MAX. 0.80 (T.P.) 0.32+0.08 -0.07 0.100.05 1.10.1 1.00 11.760.20 10.160.10 0.800.20 0.145+0.025 -0.015 0.500.10 0.13 0.10 3+7 -3 S54G5-80-9JF-2
Data Sheet E0149N10
81
PD4564441, 4564841, 4564163
15. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD4564xxx. Type of Surface Mount Device
PD4564xxxG5: 54-pin Plastic TSOP (II) (10.16mm (400))
www..com
82
Data Sheet E0149N10
PD4564441, 4564841, 4564163
16. Revision History
Edition / Date Page Previous This edition edition Type of revision Description Location
NEC Corporation (M12621E) 11th edition / April, 1999 p.19 p.19 p.15 p.15 Modification, Addition Modification, Addition p.37 p.46 p.47 p.50 p.51
www..com
CKE Truth Table - Power down
Command Truth Table for CKE - Power down
p.37 p.46 p.47 p.50 p.51 p.52 p.77 p.2, 3 p.35
Modification Modification Modification Modification Modification Modification Modification Deletion Modification Deletion
Note 1. Output load Symbol Symbol Timing Chart (Power Down Mode Exit) , Symbol Symbol Symbol Timing Chart (Precharge Command for Bank D) -AxxL ICC2PS -AxxL AC Characteristics Test Conditions Package Drawing
p.52 p.77 12th edition / January, 2000 p.2, 3 p.35
p.36 p.81 Elpida Memory, Inc. (E0149N) Ver.1.0 / August. 2001 -
p.36 p.81
Modification Modification
-
-
Republished by Elpida Memory, Inc.
Data Sheet E0149N10
83
PD4564441, 4564841, 4564163
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be www..com generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
84
Data Sheet E0149N10
PD4564441, 4564841, 4564163
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others.
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Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107

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